1. Field of the Invention
The present invention relates to a video adapter for converting an analog video signal output from a personal computer or other video signal source to a digital video signal, and relates more specifically to a video adapter that compensates for variation in the clock frequency, phase timing, and display position of the converted digital video signal, and to a digital image display apparatus comprising said video adapter.
2. Description of the Prior Art
Raster scan analog displays based on a cathode ray tube (CRT) are most commonly used as the image display means of today's personal computers. The need to save space and reduce power consumption, however, has helped drive the development of digital image displays as a replacement for analog video signals. Typical of current digital displays is the flat panel display, which include liquid crystal displays, plasma displays, and cathode-type raster scan displays.
Image signals internally generated and processed by a personal computer, however, are digital signals. An internal or external video adapter has therefore been required to convert this digital signal to an analog signal for display on an analog display device.
This means that when a digital image display is used in place of the more conventional analog image display, an internal or external video adapter must be provided for the digital image display to reconvert the analog video signal output from the personal computer to a digital video signal. For convenience in the following discussion the video adapter used by the personal computer for analog-digital conversion is below referenced as the "output video adapter," and the video adapter used by the digital image display for digital-analog conversion is referenced as the "input video adapter."
The structure and operation of a conventional input video adapter VAc is described below referring to FIG. 10. This input video adapter VAc converts the analog video signal input from a personal computer to a digital video signal (A/D converts), and generates the digital image signal Sidc and display coordinate data Dco for controlling the digital image display.
As shown in FIG. 10 the input video adapter VAc comprises an A/D converter 1, clock generation circuit 2, delay circuit 5 display control circuit 14, and preset data memory 7. The analog image signal Sia and horizontal synchronization signal Hsync contained in the analog video signal are input to the A/D converter 1 and delay circuit 5, respectively. The clock generation circuit 2 is a phase-locked loop (PLL) circuit. The delay circuit 5 is achieved by means of a delay line or method using the delay value of each element in the gate array. The preset data memory 7 stores the image adjustment parameters PI, which is a set of predefined clock count data Dcl, phase data Dph, and display coordinate data Dco for every possible image resolution level of the analog video signal that may be input from the personal computer.
The display control circuit 14 outputs the clock count data Dcl to the clock generation circuit 2, the phase data Dph to the delay circuit 5, and the display coordinate data Dco to the digital image display by reading the image adjustment parameters PI corresponding to the image resolution of the analog image signal Sia by monitoring the frequency of the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync of the input image signal.
Based on the supplied phase data Dph, the delay circuit 5 delays the horizontal synchronization signal Hsync a known period to change the signal phases and then outputs the result to the clock generation circuit 2.
The clock generation circuit 2 is a PLL circuit to which the clock count data Dcl from the display control circuit 14 is set. The clock generation circuit 2 operates at the frequency indicated by the clock count data Dcl to generate a clock CLK phase synchronized to the phase-shifted horizontal synchronization signal Hsync' output from the delay circuit 5, and outputs to the A/D converter 1.
The A/D converter 1 converts the analog image signal Sia to a digital image signal Sidc according to the timing of the clock CLK, and outputs to the display circuit (not shown in the figure) of the digital image display.
The image display is thus adjusted by reading the image adjustment parameters PI from the preset data memory 7 according to the image resolution of the analog video signal, and then outputting to the corresponding circuits. More specifically, the display control circuit 14 controls the clock CLK and the data phase relationship in the A/D converter 1 by outputting the phase data Dph (i.e., delay time) to the delay circuit 5. It should also be noted that an input means (not shown in the figures) connected to the display control circuit 14 is also provided so that the user can directly adjust the image adjustment parameters PI.
Note the image adjustment parameter PI data, specifically the clock CLK, display coordinate data Dco, and phase data Dph defined according to the clock, display, and phase timing of the analog video signal input from the personal computer, must be stored to the preset data memory 7 with the conventional input video adapter VAc described above. This means that image adjustment is not possible when an analog video signal with timing different from the timing of the image adjustment parameters PI stored to the preset data memory 7 is input, and the digital image display therefore cannot correctly display the image.
The output video adapters used with personal computers are also not completely standardized, and the timing of the analog video signals output by different video adapters and personal computers conforming to different standards often vary slightly from the "standard" timing. When this happens the clock count data Dcl, phase data Dph, and display coordinate data Dco read by the display control circuit 14 from the preset data memory 7 does not match the actually input analog video signal. This results in partial loss of or interference in the image displayed by the digital image display.
To compensate for such image flicker, jitter, or dropout the clock count data Dcl, phase data Dph, and display coordinate data Dco of the image adjustment parameters PI must be corrected according to the actually input analog video signal. This means that the user must operate keys, switches, or other input means while viewing the image displayed on the digital image display to manually adjust the image adjustment parameters PI stored in the preset data memory 7 according to the input analog video signal. This operation must be performed while visually monitoring the change in the image on a pixel level, and therefore requires both training and time. This actual image adjustment operation is described in detail below for the clock count data Dcl, phase data Dph, and display coordinate data Dco with reference to FIG. 11, FIG. 12, and FIG. 13.
Adjustment of the clock count data Dcl is described first. Note that the analog video signal input to the input video adapter VAc is assumed below to have been generated as a digital signal by a personal computer or other digital device. The original digital video signal is converted to an analog video signal using a D/A converter based on a dot clock synchronized to the horizontal synchronization signal Hsync. The converted analog video signal is supplied to a CRT monitor or other analog image display requiring an analog video signal input.
FIG. 11 shows the clock CLK and horizontal synchronization signal Hsync generated by the clock generation circuit 2. The dot clock is synchronized to the horizontal synchronization signal Hsync as described above. The A/D converter 1 sequentially converts the analog image signal Sia to a digital image signal Sidc based on the clock CLK. As a result the phase of the clock CLK must be synchronized to the phase of the horizontal synchronization signal Hsync to correctly display the image on LCD monitor or other digital image display.
Pulse Pc1 and Pcn of the clock CLK correspond to the pulse Ph1 and Ph2 of the horizontal synchronization signal Hsync where n is an integer greater than the horizontal resolution of the analog image signal Sia by a known amount. Pulse Ph1 and pulse Ph2 are positioned at the beginning and end of a particular horizontal scanning period Th. Note that the clock CLK and horizontal synchronization signal Hsync are synchronized if the starting time difference .alpha. and termination time difference .beta. are equal where the starting time difference .alpha. is the time difference between pulses Ph1 and Pc1 and the termination time difference .beta. is the time difference between pulses Ph2 and Pcn.
More specifically, adjusting the clock count data Dcl can be accomplished by changing the value of clock count data Dcl to synchronize the clock CLK to the horizontal synchronization signal Hsync, i.e., so that the difference T between starting time difference .alpha. and termination time difference .beta. equals zero (Dcl=.alpha.-.beta.=0). Whether starting time difference .alpha. and termination time difference .beta. are equal is determined by the user evaluating the quality of the image displayed on the monitor. This operation thus adjusts the offset T (Dcl) of the preset clock count data Dcl to the actual dot clock.
Adjusting the phase data Dph is described next.
The delay circuit 5 delays the horizontal synchronization signal Hsync supplied to the clock generation circuit 2 based on the phase data Dph input from the display control circuit 14. The clock generation circuit 2 generates a clock CLK phase synchronized to the delayed horizontal synchronization signal Hsync', and outputs to the A/D converter 1. The phase data Dph is thus a value specifying how much to delay the horizontal synchronization signal Hsync, and determines the timing whereby the A/D converter 1 converts the analog image signal Sia to a digital image signal Sid.
The analog image signal Sia, ideal clock CLKa, and actual clock CLKb are shown in FIG. 12. The ideal clock CLKa is the ideal timing pulse required to correctly A/D convert the analog image signal Sia. For example, if the A/D conversion timing is determined at the clock rise, the ideal clock CLKa has the rising edge Ea positioned at the middle of the pixel in the analog image signal Sia.
The phase of the actual clock CLKb, however, is shifted relative to the ideal clock CLKa, and the different T (Dph) is a maximum 180 degrees as shown in FIG. 12. In this case the rising edge Eb of the actual clock CLKb is positioned at the rise and the drop of the analog image signal Sia. A/D conversion is therefore processed around the unstable part of the analog image signal Sia, thus introducing interference to the image. To remove this interference, the actual clock CLKb must be delayed phase different T (Dph) to approach the ideal clock CLKa, or the phase difference data T (Dph) must be corrected.
To determine whether the actual clock CLKb is synchronized to the ideal clock CLKa, the user must evaluate the quality of the image displayed on the monitor. The offset T (Dph) of the preset phase data Dph of the clock CLK to the ideal clock CLKa is thus manually adjusted.
The display coordinate data Dco is described next.
The horizontal synchronization signal Hsync, analog image signal Sia, ideal image capture period Cp1, and the actual image capture period Cp2 of the image in the preceding line are shown in FIG. 13. The display coordinate data Dco determines the capture period CP of the analog image signal Sia. The analog image signal Sia also has an effective horizontal display period HEDP in the synchronization period of the horizontal synchronization signal Hsync. Note that the effective horizontal display period HEDP determines the horizontal space of the pixels to be displayed, i.e., the horizontal distance between the pixel at the left end and the pixel at the right end of the pixels displayed in each horizontal line displayed on screen. The ideal image capture period Cp1 matches the effective horizontal display period HEDP of the analog image signal Sia, resulting in all pixels being displayed.
The actual image capture period Cp2, however, is offset a specific period T (Dco) from the ideal image capture period Cp1. In other words, at the actual image capture period Cp2 the capture period CP and effective horizontal display period HEDP do not match, and the image is displayed on screen with image dropout of period T (Dco) at each edge.
To resolve this image dropout problem the actual image capture period Cp2 must be offset period T (Dco) closer to the ideal image capture period Cp1, or the display coordinate data Dco must be corrected so that the actual image capture period Cp2 matches the ideal image capture period Cp1.
In other words, whether the ideal image capture period Cp1 and the actual image capture period Cp2 match must again be determined by the user evaluating the image quality on the screen. The offset T (Dco) of the preset display coordinate data Dco of the actual image capture period Cp2 is thus manually adjusted to the ideal image capture period Cp1.
The object of the present invention is therefore to provide a method and apparatus for automatically adjusting the clock count data Dcl, phase data Dph, and display coordinate data Dco according to the actually input analog image signal Sia, thereby eliminating the training, practice, and time required by the prior art for manual adjustment of the data as described above.